1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a copper-based plug formed in a contact area of the integrated circuit to enhance overall contact conductivity.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves numerous processing steps. Using openings ("vias") to connect one conductive layer to another is well known in the art. Vias are generally formed through an insulating material disposed between conductive layers. Since minimum feature sizes of conventional integrated circuits have become more popular in industry, vias having substantially vertical sidewalls are desirable because they require less space. However, when physical vapor deposition is performed to deposit metal over vias, vertical sidewalls cause step coverage problems. Step coverage is defined as a measure of how well a film conforms over an underlying step. In this instance, step coverage over relatively vertical sidewalls of a via is problematic relative to sloped sidewalls. Step coverage is often measured as a ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film on horizontal regions. It is desired that step coverage be a large value, however, step coverage above 0.5 seems adequate in most fabrication processes. A via having a greater depth to width ratio ("aspect ratio") results in smaller step coverage of a conductive film deposited across the via. In order to implement a vertical sidewall, the via generally must be filled with a conductive material which readily flows or conforms to the via topography.
A metal deposited by chemical vapor deposition ("CVD") allows such conformance, and produces what is generally referred to in the industry as a metal "plug" formed exclusively in the via. Plug material is chosen so that it fills the via to a height commensurate with the adjacent dielectric surface. Subsequently deposited films will therefore not have to contend with severe steps of the underlying surface adjacent the via.
Tungsten is at least one of the more popular plug materials. Two CVD tungsten methods have been developed for filling vias. In one method, tungsten is selectively deposited from WF.sub.6 which can be reduced by silicon, hydrogen, or silane. When hydrogen reduction is used, selectivity occurs at a temperature below which the insulating material does not catalyze hydrogen dissociation, but at which other surfaces, e.g., silicon, metal, or silicide catalyze the dissociation. At a temperature below about 500.degree. C., tungsten may be selectively deposited upon only the bottom of a via. One limitation of the hydrogen reduction process is that hydrogen fluoride gas is a by-product which is believed to be responsible for junction leakage. The junction leakage is caused by lateral encroachment under the adjacent dielectric (i.e., oxide) and by tiny holes formed within the oxide.
Problem of selective CVD are overcome, to some degree, by a blanket CVD and etchback technique. Despite the added processing steps and the material waste involved in depositing and thereafter removing sacrificial portions of tungsten, blanket deposit/etchback has become a processing mainstay. Blanket CVD involves forming an adhesion layer, e.g., titanium or titanium nitride upon the base and sidewalls of the via. This adhesion layer is necessary since tungsten deposited by CVD does not adhere well to most dielectrics. Then a layer of tungsten is deposited onto the entire surface of the semiconductor topography, and especially into the via. The tungsten is then removed in areas exclusive of the via, thereby creating a tungsten plug.
Tungsten plugs readily bond with the underlying titanium silicide. There are several problems that can result from using CVD of tungsten to form plugs within the vias. A TiF.sub.3 layer often forms at the tungsten/titanium silicide interface when selective deposition of tungsten is performed in a hotwall process at 300-350.degree. C. This layer causes contact resistance between the plug and the underlying silicide to increase relative to not having a TiF.sub.3 layer therebetween. Tungsten depositions at 600-700.degree. C. exhibit a lower contact resistance than at the lower temperature process, but some contacts formed this way demonstrate lateral outgrowth or migration of the tungsten near the base of the dielectric.
Aluminum plugs are also fairly common. However, aluminum often exhibits problems of electromigration. Electromigration is defined as the motion of ions in response to the passage of current. The ionic flux which occurs during electromigration of aluminum causes an accumulation of vacancies, forming a void within the metal. Such voids may become so large that an open-circuit failure of the conductor may occur. Furthermore, electromigration can occur as a result of current flow through an area near the silicon/aluminum interface. This involves silicon atoms moving along the grain boundaries of the aluminum plug, causing the formation of voids in the underlying silicon. Aluminum can fill the voids, leading to localized areas of the plug void of aluminum (i.e., an open circuit failure), or to aluminum extending downward through the underlying junction (i.e., junction spiking). Tungsten is more resistant to electromigration than aluminum, but electromigration of tungsten is still a problem. Resistivity of a metal increases when electromigration occurs because voids form through which charged carriers cannot pass.
Another problem resulting from using aluminum as a contact plug is that hillock formation often occurs in aluminum. Hillocks are spike-like projections that protrude from the plug surface in response to a state of compressive stress in the film. One reason for hillock formation in aluminum is that the thermal coefficient of expansion of aluminum is much larger than that of silicon. When a silicon wafer is heated, overlying aluminum desires to expand more than is allowed by the underlying wafer topography. A compressive stress in the aluminum increases as a function of temperature. Hillock growth also results from vacancy migration within a metal having a vacancy-concentration gradient. As discussed previously, aluminum exhibits electromigration which can cause this type of gradient. The rate of diffusion of vacancies increases as temperature increases. Hillocks can lead to interlevel shorting when they penetrate a dielectric layer adjacent a via and make contact with the next level of metal.